The present invention relates generally to the fabrication of semiconductor devices, and more particularly, to a de-lamination resistant bond pad structure.
In a typical integrated circuit chip, active circuit elements such as transistors, resistors, etc., are positioned in the central portion, i.e., the active region, of the chip whilst the bond pads are normally arranged around the periphery of the active region such that active circuit elements are not likely to be damaged during a subsequent bonding process. When a wire bonding process is performed on a bond pad of a chip, the process normally entails the bonding of a gold or aluminum wire to the bond pad by fusing the two together with ultrasonic energy, for example. The wire is then pulled away from the bond pad after the bond is formed. During the bonding of the wire to the pad and the pulling away of the wire from the pad, high mechanical stress is placed on the bond pad. When the bond pads are not properly formed, defects such as de-lamination of the bond pad from underlying layers of the chip have been encountered. This occurs due to the fact that during the attachment of the wire to the bond pad, a high level of mechanical stress is placed on the bond pad. It occurs when a relatively large, heavy bond is placed on top of layers, which may not have strong adhesion to the underlying layers. For instance, one factor that may affect adhesion between the layers is the use of low dielectric constant (low-k) materials that cause adhesion problems between these low-k dielectric materials and the underlying oxide layers. The adhesion of low-k dielectric material, or inter-metal-dielectric (IMD) material to oxide is poorer than that of oxide to oxide. The use of low-k dielectric materials, such as HSQ (hydrogen silsesquioxane) and MSQ (methylsilsesquioxane) have been desirable in high performance semiconductor structures since due to their low-k characteristics, thinner layers of the materials may be utilized as insulating layers. Another drawback of these low-k dielectric materials is their low thermal conductivity when compared to that of regular oxide. During a chip bonding process, the local temperature around a bond pad is significantly higher due to the poor thermal conductivity of the low-k dielectric material. The thermal stress caused by the poor thermal conductivity of IMD, in addition to the mechanical stresses caused by the bonding operation, may cause de-lamination of the low-k IMD layers from their underlying oxide layers.
One conventional method for overcoming such increased de-lamination characteristics provides for the forming of a polysilicon pattern under a bond pad to prevent the bond pad from peeling during subsequent manufacturing processes. The use of a polysilicon interface between the metal bond pad and the interlayer dielectric prevents bond pad peeling or lifting by having chemically compatible interlayer surfaces, thereby providing attendant increased adhesive properties. However, a significant disadvantage is that the polysilicon layer is typically deposited directly over a layer of insulating material rather than over a layer of a metallic material, thereby providing adhesion and anchoring characteristics that are not optimal. Various other approaches to solving the de-lamination and poor thermal conductivity issues require additional fabrication process steps during the fabrication of the bond pads.
For these reasons and other reasons that will become apparent upon reading the following detailed description, there is a need for an improved bond pad structure that avoids the de-lamination and thermal conductivity problems associated with conventional bond pad structures.